1 ps8418h 01/25/06 pin confguration block diagram pi6c2402 features ? clock doubler ? high-performance phase-locked-loop clock distribution for networking, atm, 100 mhz and 134 mhz registered dimm synchronous dram modules for server, workstation, and pc applications ? zero input-to-output delay ? cycle-to-cycle jitter 150ps max. ? on-chip series damping resistor at clock output drivers for low noise and emi reduction ? operates at 3.3v v cc ? packaging (pb-free & green available): 8-pin soic package (w) phase-locked loop clock driver description the pi6c2402 features a low-skew, low-jitter, phase-locked loop (pll) clock driver. by connecting the feedback clk_out out - put to the feedback fb_in input, the propagation delay from the clk_in input to any clock output will be nearly zero. the pi6c2402 provides 2x clk_in on clk_out output. applications if the system designer needs more than 16 outputs with the fea - tures just described, using two or more zero-delay buffers such as the pi6c2509, and the pi6c2510, are likely to be impractical. the device-to-device skew introduced can signifcantly reduce the performance. pericom recommends the use of a zero-delay buffer and an eighteen output non-zero-delay buffer. as shown in figure 1, this combination produces a zero-delay buffer with all the signal characteristics of the original zero-delay buffer, but with as many outputs as the non-zero-delay buffer part. for example, when combined with an eighteen output non-zero delay buffer, a system designer can create a seventeen-output zero-delay buffer. figure 1. zero-delay buffering diagram 17 zero delay buf fer pi6c2402 reference clock signal clk_out feedback 18 output non-zero delay buf fer v control input s outputs source pll shutdown high pll disabled low clk_in enabled clk_in fb_in s pll clk_out 2 1 2 3 av cc 4 clk_out clk_in gnd fb_in 8 7 6 5 agnd v cc s
pi6c2402 phase-locked loop clock driver 2 ps8418h 01/25/06 recommended operating conditions symbol test conditions temperature min. max. units v cc supply voltage commercial 3.0 3.6 v industrial 3.135 3.465 v ih high level input voltage 2.0 v il low level input voltage 0.8 v i input voltage 0 v cc t a operating free-air temperature commercial 0 70 oc industrial -40 85 absolute maximum ratings (1) (over operating free-air temperature range) symbol test conditions min. max. units v i input voltage range -0.5 v cc + 0.5 v v o output voltage range -0.5 v cc + 0.5 vi_dc dc input voltage -0.5 5.0 io_dc dc output current 100 ma power maximum power dissipation at ta = 55oc in still air 1.0 w t stg storage temperature -65 150 oc pin functions name number type description clk_in 1 i reference clock inptu, clk_in allows spread spectrum clock input av cc 2 power analog power agnd 3 ground analog ground clk_out 4 o clock output. the output provides low-skew copies of clk_in and has an embedded series-damping resistor. s 5 i control input s. s is used to bypass the pll for test purposes. when s is strapped to ground, pll is bypassed and clk_in is buffered directly to the device outputs gnd 6 ground ground v cc 7 power power supply fb_in 8 i feedback input. fb_in provides the feedback signal to the internal pll. note: 1. stress beyond those listed under absolute maximum ratings may cause permanent damage to the device.
pi6c2402 phase-locked loop clock driver 3 ps8418h 01/25/06 ac specifcations timing requirements (over recommended ranges of supply voltage and operating free-air temperature, c l = 25pf) symbol parameters test conditions min. typ. max. units f out clock frequency commercial 25 134 mhz industrial 25 100 d cyi input clock duty cycle 40 60 % stabilization time after power up 1 ms t p phase error without jitter (1) clk_in at 100 mhz and 66 mhz -150 150 ps t j jitter, cycle-to-cycle at 100 mhz -150 150 duty cycle at 100 mhz 45 55 % at > 100 mhz 35 65 t r rise-time 0.4v to 2.0v 1.0 ns t f fall-time 2.0v to 0.4v 1.1 electrical characteristics (over recommended operating free-air temperature range) symbol test conditions temperature condition min. typ. max. units i cc v i = gnd; io = 0 (1) commercial 3.6v 10 a industrial 3.465v 10 c i v i = v cc or gnd 3.3v 4 pf c o v o = v cc or gnd 3.3v 6 i oh v out = 2.4v -12 ma v out = 2.0v -18 iol v out = 0.8v 18 v out = 0.55v 12 note: 1. continuous output current note: 1. this switching parameter is guaranteed by design.
pi6c2402 phase-locked loop clock driver 4 ps8418h 01/25/06 packaging mechanical: 8-pin plastic soic (w) ordering information (1,2,3) pericom semiconductor corporation ? 1-800-435-2336 ? www.pericom.com notes: 1. thermal characteristics can be found on the company web site at www .pericom.com/packaging/ 2. e = pb-free & green 3. x suffx = tape/reel ordering code package code package description PI6C2402W w 8-pin, 150-mil soic PI6C2402We w pb-free & green, 8-pin, 150-mil soic PI6C2402Wi w 8-pin, 150-mil soic PI6C2402Wie w pb-free & green, 8-pin, 150-mil soic ????? ????? ??? ?????????? ???? ???? ???? ??? ???? ????? ????? ? ? ????? ????? ???? ???? ???? ???? ???? ???? ???? ?????????????? ?????????????? ???? ???? ???? ???? ???? ???? ???? ????? ???? ???? ???? ????? ????? ???? ???? ????? ????? ????? ????? ???? ???? ???? ???? ???? ???? ???? ???? ????? ???? ???? ???
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